Registers:
Register Bits Description
D 8 Data Register
DF 1 Data Flag (carry/borrow)
R(0-f) 16 General Registers
P 4 Specifies which R register is program counter
X 4 Specifies which R register is data pointer
I 4 High nybble of instruction byte, not directly accessable
N 4 Low nybble of instruction byte, not directly accessable
T 8 Holds X and P during interrupt, X is high nybble, not directly accessable
IE 1 Interrupt Enable
Q 1 Output Flip/Flop
Opcode Mnemonic Instruction Operation
0NLDNLoad via NM(R(N))->D; For N not 0
4NLDALoad AdvanceM(R(N))->D; R(N)+1->R(N)
F0LDXLoad via XM(R(X))->D
72LDXALoad via X and advanceM(R(X))->D; R(X)+1->R(X)
F8LDILoad immediateM(R(P))->D; R(P)+1->R(P)
5NSTRStore via ND->M(R(N))
73STXDStore Via X and dec.D->M(R(X)); R(X)-1->R(X)
1NINCIncrement reg NR(N)+1->R(N)
2NDECDecrement reg NR(N)-1->R(N)
60IRXIncrement reg XR(X)+1->R(X)
8NGLOGet low reg NR(N).0->D
ANPLOPut low reg ND->R(N).0
9NGHIGet high reg NR(N).1->D
BNPHIPut high reg ND->R(N).1
F1OROrM(R(X)) or D->D
F9ORIOr immediateM(R(P)) or D->D; R(P)+1->R(P)
F3XORExclusive orM(R(X)) xor D->D
FBXRIExclusive or immediateM(R(P)) xor D->D; R(P)+1->R(P)
F2ANDAndM(R(X)) and D->D
FAANIAnd immediateM(R(P)) and D->D; R(P)+1->R(P)
F6SHRShift rightShift D right; lsb(D)->DF;
0->msb(D)
76SHRCShift right with carryShift D right; lsb(D)->DF;
DF->msb(D)
FESHLShift leftShift D left; msb(D)->DF;
0->lsb(D)
7ESHLCShift left with carryShift D left; msb(D)->DF;
DF->lsb(D)
F4ADDAddM(R(X))+D->DF,D
FCADIAdd immediateM(R(P))+D->DF,D; R(P)+1->R(P)
74ADCAdd with carryM(R(X))+D+DF->DF,D
7CADCIAdd with carry imm.M(R(P))+D+DF->DF,D; R(P)+1->R(P)
F5SDSubtract DM(R(X))-D->DF,D
FDSDISubtract D immediateM(R(P))-D->DF,D; R(P)+1->R(P)
75SDBSub. D with borrowM(R(X))-D-DF->DF,D
7DSDBISub. D with borrow imm.M(R(P))-D-DF->DF,D; R(P)+1->R(P)
F7SMSubtract memoryD-M(R(X))->DF,D
FFSMISubtract Mem. imm.D-M(R(P))->DF,D; R(P)+1->R(P)
77SMBSub. Mem. with borrowD-M(R(X))-DF->DF,D;
7FSMBISub. Mem. w/borrow imm.D-M(R(P))-DF->DF,D; R(P)+1>R(P)
30BRBranchM(R(P))->R(P).0
38NBRNo BranchR(P)+1->R(P)
32BZBranch if D=0If D=0, M(R(P))->R(P).0
else R(P)+1->R(P)
3ABNZBranch if D<>0If D<>0, M(R(P))->R(P).0
else R(P)+1->R(P)
33BDFBranch if DF=1if DF=1, M(R(P))->R(P).0
else R(P)+1->R(P)
3BBNFBranch if DF=0if DF=0, M(R(P))->R(P).0
else R(P)+1->R(P)
31BQBranch if Q=1if Q=1, M(R(P))->R(P).0
else R(P)+1->R(P)
39BNQBranch if Q=0if Q=0, M(R(P))->R(P).0
else R(P)+1->R(P)
34B1Branch if EF1=1if EF1=1, M(R(P))->R(P).0
else R(P)+1->R(P)
3CBN1Branch if EF1=0if EF1=0, M(R(P))->R(P).0
else R(P)+1->R(P)
35B2Branch if EF2=1if EF2=1, M(R(P))->R(P).0
else R(P)+1->R(P)
3DBN2Branch if EF2=0if EF2=0, M(R(P))->R(P).0
else R(P)+1->R(P)
36B3Branch if EF3=1if EF3=1, M(R(P))->R(P).0
else R(P)+1->R(P)
3EBN3Branch if EF3=0if EF3=0, M(R(P))->R(P).0
else R(P)+1->R(P)
37B4Branch if EF4=1if EF4=1, M(R(P))->R(P).0
else R(P)+1->R(P)
3FBN4Branch if EF4=0if EF4=0, M(R(P))->R(P).0
C0LBRLong BranchM(R(P))->R(P).1;
M(R(P)+1)->R(P).0
C8NLBRNo long branchR(P)+2->R(P)
C2LBZBranch if D=0if D=0 then M(R(P))->R(P).1;
M(R(P)+1)->R(P).0
else R(P)+2->R(P)
CALBNZBranch if D<>0if D<>0 then M(R(P))->R(P).1;
M(R(P)+1)->R(P).0
else R(P)+2->R(P)
C3LBDFBranch if DF=1if DF=1 then M(R(P))->R(P).1;
M(R(P)+1)->R(P).0
else R(P)+2->R(P)
CBLBNFBranch if DF=0if DF=0 then M(R(P))->R(P).1;
M(R(P)+1)->R(P).0
else R(P)+2->R(P)
C1LBQBranch if Q=1if Q=1 then M(R(P))->R(P).1;
M(R(P)+1)->R(P).0
else R(P)+2->R(P)
C9LBNQBranch if Q=0if Q=0 then M(R(P))->R(P).1;
M(R(P)+1)->R(P).0
else R(P)+2->R(P)
CELSZSkip if D=0if D=0, R(P)+2->R(P)
else Continue
C6LSNZSkip if D<>0if D<>0, R(P)+2->R(P)
else Continue
CFLSDFSkip if DF=1if DF=1, R(P)+2->R(P)
else Continue
C7LSNFSkip if DF=0if DF=0, R(P)+2->R(P)
else Continue
CDLSQSkip if Q=1if Q=1, R(P)+2->R(P)
else Continue
C5LSNQSkip if Q=0if Q=0, R(P)+2->R(P)
else Continue
CCLSIESkip if IE=1if IE=0, R(P)+2->R(P)
else Continue
00IDLIdleWait for DMA or Interrupt
M(R(0))->Bus
C4NOPNo operationContinue
DNSEPSet PN->P
ENSEXSet XN->X
7BSEQSet Q1->Q
7AREQReset Q0->Q
78SAVSaveT->M(R(X))
79MARKPush X,P to stack(X,P)->T; (X,P)->M(R(2)) then
P->X; R(2)-1->R(2)
70RETReturnM(R(X))->(X,P); R(X)+1->R(X); 1->IE
71DISDisableM(R(X))->(X,P); R(X)+1->R(X); 0->IE
61OUT1Output 1M(R(X))->Bus; R(X)+1->R(X); Nlines=1
62OUT1Output 2M(R(X))->Bus; R(X)+1->R(X); Nlines=2
63OUT1Output 3M(R(X))->Bus; R(X)+1->R(X); Nlines=3
64OUT1Output 4M(R(X))->Bus; R(X)+1->R(X); Nlines=4
65OUT1Output 5M(R(X))->Bus; R(X)+1->R(X); Nlines=5
66OUT1Output 6M(R(X))->Bus; R(X)+1->R(X); Nlines=6
67OUT1Output 7M(R(X))->Bus; R(X)+1->R(X); Nlines=7
69INP1Input 1Bus->M(R(X)); Bus->D; Nlines=1
6AINP1Input 2Bus->M(R(X)); Bus->D; Nlines=2
6BINP1Input 3Bus->M(R(X)); Bus->D; Nlines=3
6CINP1Input 4Bus->M(R(X)); Bus->D; Nlines=4
6DINP1Input 5Bus->M(R(X)); Bus->D; Nlines=5
6EINP1Input 6Bus->M(R(X)); Bus->D; Nlines=6
6FINP1Input 7Bus->M(R(X)); Bus->D; Nlines=7
Reverse Opcode Table: 1802
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 IDL LDN 1 LDN 2 LDN 3 LDN 4 LDN 5 LDN 6 LDN 7 LDN 8 LDN 9 LDN A LDN B LDN C LDN D LDN E LDN F
1 INC 0 INC 1 INC 2 INC 3 INC 4 INC 5 INC 6 INC 7 INC 8 INC 9 INC A INC B INC C INC D INC E INC F
2 DEC 0 DEC 1 DEC 2 DEC 3 DEC 4 DEC 5 DEC 6 DEC 7 DEC 8 DEC 9 DEC A DEC B DEC C DEC D DEC E DEC F
3 BR BQ BZ BDF B1 B2 B3 B4 NBR BNQ BNZ BNF BN1 BN2 BN3 BN4
4 LDA 0 LDA 1 LDA 2 LDA 3 LDA 4 LDA 5 LDA 6 LDA 7 LDA 8 LDA 9 LDA A LDA B LDA C LDA D LDA E LDA F
5 STR 0 STR 1 STR 2 STR 3 STR 4 STR 5 STR 6 STR 7 STR 8 STR 9 STR A STR B STR C STR D STR E STR F
6 IRX OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 --- INP 1 INP 2 INP 3 INP 4 INP 5 INP 6 INP 7
7 RET DIS LDXA STXD ADC SDB SHRC SMB SAV MARK REQ SEQ ADCI SDBI SHLC SMBI
8 GLO 0 GLO 1 GLO 2 GLO 3 GLO 4 GLO 5 GLO 6 GLO 7 GLO 8 GLO 9 GLO A GLO B GLO C GLO D GLO E GLO F
9 GHI 0 GHI 1 GHI 2 GHI 3 GHI 4 GHI 5 GHI 6 GHI 7 GHI 8 GHI 9 GHI A GHI B GHI C GHI D GHI E GHI F
A PLO 0 PLO 1 PLO 2 PLO 3 PLO 4 PLO 5 PLO 6 PLO 7 PLO 8 PLO 9 PLO A PLO B PLO C PLO D PLO E PLO F
B PHI 0 PHI 1 PHI 2 PHI 3 PHI 4 PHI 5 PHI 6 PHI 7 PHI 8 PHI 9 PHI A PHI B PHI C PHI D PHI E PHI F
C LBR LBQ LBZ LBDF NOP LSNQ LSNZ LSNF NLBR LBNQ LBNZ LBNF LSIE LSQ LSZ LSDF
D SEP 0 SEP 1 SEP 2 SEP 3 SEP 4 SEP 5 SEP 6 SEP 7 SEP 8 SEP 9 SEP A SEP B SEP C SEP D SEP E SEP F
E SEX 0 SEX 1 SEX 2 SEX 3 SEX 4 SEX 5 SEX 6 SEX 7 SEX 8 SEX 9 SEX A SEX B SEX C SEX D SEX E SEX F
F LDX OR AND XOR ADD SD SHR SM LDI ORI ANI XRI ADI SDI SHL SMI

1805 Extended Instructions:
Opcode Mnemonic Instruction Operation
68 CNRLDIRegister load immed. M(R(P))->R(N).1; M(R(P)+1)->R(N).0; R(P)+2->R(P)
68 6NRLXARegister load via X, Adv. M(R(X))->R(N).1; M(R(X)+1)->R(N).0; R(X)+2->R(X)
68 ANRSXDRegister store via X, Dec. R(N).0->M(R(X)); R(N).1->M(R(X)-1); R(X)-2->R(X)
68 2NDBNZDec reg N, LBR if not 0 R(N)-1->R(N); if R(N) not 0,M(R(P))->R(P).1;M(R(P)+1)->R(P).0
else R(P)+2->R(P)
68 BNRNXRegister N to X copy R(N)->R(X)
68 F4DADDDecimal Add M(R(X))+D->DF,D, decimal adjust
68 FCDADIDecimal Add Immed. M(R(P))+D->DF,D, decimal adjust; R(P)+1->R(P)
68 74DADCDecimal Add with carry M(R(X))+D+DF->DF,D, decimal adjust
68 7CDACIDecimal Add Immed. with carry M(R(P))+D+DF->DF,D, decimal adjust; R(P)+1->R(P)
68 F7DSMDecimal sub memory D-M(R(X))->DF,D, decimal adjust
68 FFDSMIDecimal sub Immed D-M(R(P))->DF,D, decimal adjust; R(P)+1->R(P)
68 77DSMBDecimal sub memory w/borrow D-M(R(X))-(not DF)->DF,D, decimal adjust
68 7FDSBIDecimal sub Immed w/borrow D-M(R(P))-(not DF)->DF,D, decimal adjust; R(P)+1->R(P)
68 3EBCIShort branch on counter int if CI=1,M(R(P))->R(P).0; 0->CI
else R(P)+1->R(P)
68 3FBXIShort branch on external int if XI=1,M(R(P))->R(P).0; 0->XI
else R(P)+1->R(P)
68 06LDCLoad counter Cntr stopped:D->CH,CNTR;0->CI
Cntr running:D->CH
68 08GECGet counter Cntr->D
68 00STPCStop counter Stop Cntr; 0->/32 prescaler
68 01DTCDecrement counter Cntr-1->Cntr
68 07STMSet timer mode and start TPA/32->Cntr
68 05SCM1Set counter mode 1 and start /EF1->Cntr clock
68 03SCM2Set counter mode 2 and start /EF2->Cntr clock
68 04SPM1Set pulse width mode 1 and start TPA.EF1>Cntr clock, /EF1 / stops count
68 02SPM2Set pulse width mode 2 and start TPA.EF2>Cntr clock, /EF2 / stops count
68 09ETQEnable toggle Q if Cntr=1; next Cntr clock / /Q->Q
68 0AXIEExternal int enable 1->XIE
68 0BXIDExternal int disable 0->XIE
68 0CCIECounter int enable 1->CIE
68 0DCIDCounter int disable 0->CIE
68 76DSAVSave T,D,DF R(X)-1->R(X); T->M(R(X))
R(X)-1->R(X); D->M(R(X))
Shift D right with carry
R(X)-1->R(X); D->M(R(X))
68 8NSCALStandard call R(N).0->M(R(X)); R(N).1->M(R(X)-1)
R(X)-2->R(X); R(P)->R(N)
M(R(N))->R(P).1
M(R(N)+1)->R(P).0
R(N)+2->R(N)
68 9NSRETStandard return R(N)->R(P)
M(R(X)+1)->R(N).1; M(R(X)+2)->R(N).0
R(X)+2->R(X)

Reverse Opcode Table: 1805 extended (68) instructions
0 1 2 3 4 5 6 7 8 9 A B C D E F
0 STPC DTC SPM2 SCM2 SPM1 SCM1 LDC STM GEC ETQ XIE XID CIE CID --- ---
1 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
2 DBNZ DBNZ DBNZ DBNZ DBNZ DBNZ DBNZ DBNZ DBNZ DBNZ DBNZ DBNZ DBNZ DBNZ DBNZ DBNZ
3 --- --- --- --- --- --- --- --- --- --- --- --- --- --- BCI BXI
4 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
5 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
6 RLXA RLXA RLXA RLXA RLXA RLXA RLXA RLXA RLXA RLXA RLXA RLXA RLXA RLXA RLXA RLXA
7 --- --- --- --- DADC --- DSAV DSMB --- --- --- --- DACI --- --- DSBI
8 SCAL SCAL SCAL SCAL SCAL SCAL SCAL SCAL SCAL SCAL SCAL SCAL SCAL SCAL SCAL SCAL
9 SRET SRET SRET SRET SRET SRET SRET SRET SRET SRET SRET SRET SRET SRET SRET SRET
A RSXD RSXD RSXD RSXD RSXD RSXD RSXD RSXD RSXD RSXD RSXD RSXD RSXD RSXD RSXD RSXD
B RNX RNX RNX RNX RNX RNX RNX RNX RNX RNX RNX RNX RNX RNX RNX RNX
C RLDI RLDI RLDI RLDI RLDI RLDI RLDI RLDI RLDI RLDI RLDI RLDI RLDI RLDI RLDI RLDI
D --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
E --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
F --- --- --- --- DADD --- --- DSM --- --- --- --- DADI --- --- DSMI